Jinkwon Kim, Ph.D.

Email: coco@kaist.ac.kr

Research Interests

• • Computer Architecture

  • Compressed DRAM/Cache

  • Sparse Tensor Accelerator

Publications

• Jinkwon Kim, Myeongjae Jang, Haejin Nam, and Soontae Kim, "HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator," IEEE/ACM International Symposium on Microarchitecture (MICRO'23).

• Myeongjae Jang, Jinkwon Kim, Haejin Nam, and Soontae Kim, "Zero and Narrow-width Value-aware Compression for Quantized Convolutional Neural Networks," to appear in IEEE Transactions on Computers (TC), 2023.

• Mincheol Kang, Wonyoung Lee, Jinkwon Kim, and Soontae Kim, "PR-SSD: Maximizing Partial Read Potential By Exploiting Compression and Channel-Level Parallelism", IEEE Transactions on Computers (TC), Vol. 72, No. 3, pp.772-785, Mar.2023.

• Myeongjae Jang, Jinkwon Kim, Jesung Kim, and Soontae Kim, "ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks," accepted for Design, Automation, and Test in Europe Conference (DATE'22).

• Jinkwon Kim, Mincheol Kang, Jeongkyu Hong, and Soontae Kim, "Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data," accepted for IEEE International Symposium on High-Performance Computer Architecture (HPCA'22).

• Jinkwon Kim, Seokin Hong, Jeongkyu Hong, and Soontae Kim, "CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems," IEEE Transactions on Computers (TC), Vol. 70, No. 7, pp.1132-1145, Jul. 2021.Jul. 2021.