Publications

Journals

• 2024

  • Myeongjae Jang, Jinkwon Kim, Haejin Nam, and Soontae Kim, "Zero and Narrow-width Value-aware Compression for Quantized Convolutional Neural Networks," IEEE Transactions on Computers (TC), Vol. 73, No. 1, pp.249-262, Jan. 2024.

  • Wonyoung Lee, Mincheol Kang, and Soontae Kim, "Highly VM-Scalable SSD in Cloud Storage Systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 43, No. 1, Jan. 2024.

• 2023

  • Jesung Kim, Mincheol Kang, Bohun Seo, Jeongkyu Hong, and Soontae Kim. "Effective Emoticon Suggestion Technique Based on Active Emotional Input Using Facial Expressions and Heart Rate Signals," Sensors 23, no. 9, May. 2023.

  • Mincheol Kang, Wonyoung Lee, Jinkwon Kim, and Soontae Kim, "PR-SSD: Maximizing Partial Read Potential By Exploiting Compression and Channel-Level Parallelism",  IEEE Transactions on Computers (TC), Vol. 72, No. 3, pp.772-785, Mar.2023.

• 2022

  • Jesung Kim, Wonyoung Lee, Jeongkyu Hong, and Soontae Kim. "Efficient Integrity-Tree Structure for Convolutional Neural Networks through Frequent Counter Overflow Prevention in Secure Memories." Sensors 22, no. 22, Nov. 2022.

• 2021

  • Imran Fareed, Mincheol Kang, Wonyoung Lee, and Soontae Kim, "Update Frequency-directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 40, No. 12 pp. 2467-2480, Dec. 2021. 

  • Jinkwon Kim, Seokin Hong, Jeongkyu Hong, and Soontae Kim, "CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems," IEEE Transactions on Computers (TC), Vol. 70, No. 7, pp.1132-1145, Jul. 2021.

  • Jungwoo Park, Soontae Kim, and Jong-Uk Hou, "An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance," ELECTRONICS, Vol. 28, No. 6, pp. 1357-1370, Jun. 2021.

  • Hamed Farbeh, Leila Delshadtehrani, Hyeonggyu Kim, and Soontae Kim, "ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories," IEEE Transactions on Computers (TC), Vol. 10, No. 11, pp. 640-654, Apr. 2021.

• 2020

• • Muhammad Avais Qureshi, Jungwoo Park, and Soontae Kim, "SALE: Smartly Allocating Low-Cost Many-bit ECC for Mitigating Read and Write Errors in STT-RAM Caches," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 28, No. 6, pp. 1357-1370, Jun. 2020.

• 2019

• • Myoungjun Lee and Soontae Kim, "Time-sensitivity-aware shared cache architecture for multi-core embedded systems,"  The Journal of Supercomputing, Vol. 75, No. 10, pp. 6746-6776, Oct. 2019.

  • Wonyoung Lee, Mincheol Kang, Seokin Hong, and Soontae Kim, "Inter-Page-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No. 9, pp. 2033-2045, Sept. 2019.

  • Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, and Jeongkyu Hong, "MH Cache: A Multi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems," ACM Transactions on Architecture and Code Optimization (TACO), Vol. 16, No. 3, Aug. 2019.

  • Muhammad Avais Qureshi, Hyeonggyu Kim, and Soontae Kim, "A Restore-free Mode for MLC STT-RAM Caches," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 27, No. 6, pp. 1465-1469, Jun. 2019.

• 2018

• • Bohun Seo*, Hyeonggyu Kim*, and Soontae Kim, "Freezing: Eliminating Unnecessary Drawing Computation for Low Power," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 39, No. 1 pp. 56-61, Jun. 2020. (*equal contribution)

  • Mincheol Kang, Wonyoung Lee, and Soontae Kim, "Subpage-aware Solid State Drive for Improving Lifetime and Performance," IEEE Transactions on Computers (TC), Vol. 67, No. 10, pp. 1492-1505, Oct. 2018.

  • Hyeonggyu Kim, Minho Ju, and Soontae Kim, "OnNetwork+: Network Delay-Aware Management for Mobile Systems," ACM Transactions on Embedded Computing Systems (TECS), Vol. 17, No. 3, Article 64, Jun. 2018.

• 2017

• • Jesung Kim, Jongmin Lee, and Soontae Kim, "TLB Index-based Tagging for Reducing Data Cache and TLB Energy Consumption," IEEE Transactions on Computers (TC), Vol. 66, No. 7, pp. 1200-1211, Jul. 2017.

  • Hyeonggyu Kim, Soontae Kim, and Jooheung Lee, "Write-Amount-Aware Management Policies for STT-RAM Caches," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 4, pp. 1588-1592, Apr. 2017.

  • Jungwoo Park, Jongmin Lee, and Soontae Kim, "A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 3, pp. 793-805, Mar. 2017.

  • Jeongkyu Hong and Soontae Kim, "Smart ECC Allocation Cache Utilizing Cache Data Space," IEEE Transactions on Computers (TC), Vol. 66, No. 2, pp. 368-374, Feb. 2017.

• 2016

• • Hamed Farbeh, Hyeonggyu Kim, Seyed Ghassem Miremadi, and Soontae Kim, "Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches," IEEE Transactions on Computers (TC), Vol. 65, No. 12, pp. 3661-3675, Dec. 2016.

  • Yebin Lee and Soontae Kim, "RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving," IEEE Transactions on Computers (TC), Vol. 65, No. 10, pp. 3210-3216, Oct. 2016.

  • Seokin Hong and Soontae Kim, "Designing A Resilient L1 Cache Architecture to Process Variation-induced Access-time Failures," IEEE Transactions on Computers (TC), Vol. 65, No. 10, pp. 2999-3012, Oct. 2016.

  • Jeongkyu Hong and Soontae Kim, "Flexible ECC Management for Low-cost Transient Error Protection of Last-Level Caches," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 6, pp. 2152-2164, Jun. 2016.

  • Yebin Lee and Soontae Kim, "CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 5, pp. 1770-1782, May 2016.

  • Jongmin Lee and Soontae Kim, "Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 3, pp. 871-883, Mar. 2016.

• 2015

• • Seokin Hong and Soontae Kim, "A Low-cost Mechanism Exploiting Narrow-width Values for Tolerating Hard Faults in ALU," IEEE Transactions on Computers (TC), Vol. 64, No. 9, pp. 2433-2446, Sep. 2015.

  • Jongmin Lee and Soontae Kim, "Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven by Miss Cost Reduction," IEEE Transactions on Computers (TC), Vol. 64, No. 7, pp. 1927-1939, Jul. 2015.

  • Tayyeb Mahmood, Seokin Hong, and Soontae Kim, "Ensuring cache reliability and energy scaling at near-threshold voltage with Macho," IEEE Transactions on Computers (TC), Vol. 64, No. 6, pp. 1694-1706, Jun. 2015.

  • Jeongkyu Hong*, Jesung Kim*, and Soontae Kim, "Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories," IEEE Transactions on VLSI Systems (TVLSI), Vol. 23, No. 2, pp. 254-265, Feb. 2015. (*equal contribution)

  • Mohammad Rouf and Soontae Kim, "Low-cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline," IEEE Transactions on VLSI Systems (TVLSI), Vol. 23, No. 1, pp. 131-141, Jan. 2015.

• 2013

• • Gieil Lee, Soontae Kim, and Jooheung Lee, "Software-Pipelined Academy, Research Institute, and Agency on a 64-bit Superscalar Processor for High Performance," Sensor Letters, Vol. 11, No. 9, pp. 1804-1813, Sep. 2013.

  • Tayyeb Mahmood and Soontae Kim, "Fault Buffers Enabling Near-True Voltage Scaling in Variation-Sensitive L1 Caches," Design Automation for Embedded Systems (DAEM), Vol. 17, No. 2, pp. 411–438, Jun. 2013.

• 2012

• • Kwangcheol Shin and Soontae Kim, "Predictive Routing for Mobile Sinks in Wireless Sensor Networks: A Milestone-based Approach," Journal of Supercomputing, Vol. 62, No. 3, pp. 1519–1536, Dec. 2012.

  • Kwangcheol Shin, Kyungjun Kim, and Soontae Kim, "Traffic Management Strategy for Delay-Tolerant Networks," Journal of Network and Computer Applications, Vol. 35, No. 6, pp. 1762-1770, Nov. 2012.

  • Divyan Munirathnam Konidala, Made Harta Dwijaksara, Kwangjo Kim, Dongman Lee, Byoungcheon Lee, Daeyoung Kim and Soontae Kim, "Resuscitating privacy-preserving mobile payment with customer in complete control," Journal of Personal and Ubiquitous Computing (PUC), Vol. 16, No. 6, pp. 643-654, Aug. 2012.

  • Jooheung Lee, Chul Ryu, and Soontae Kim, "Self-reconfigurable approach for computation-intensive motion estimation algorithm in H.264/AVC," Optical Engineering, 51(4), 047008, Apr. 2012.

• 2011

• • Kwangcheol Shin and Soontae Kim, "Enhanced buffer management Policy that utilizes message properties for delay-tolerant networks," IET Communication, Vol. 5, No. 6, pp. 753-759, 2011.

• 2009

• • Soontae Kim, "Reducing Area Overhead for Error-Protecting Large L2/L3 Caches," IEEE Transactions on Computers (TC), Vol. 58, No. 3, pp. 300-310, March 2009.

  • K. Bhattacharya, N.Ranganathan, and Soontae Kim, "A Framework for Correction of Multi-bit Soft Errors in L2 Caches Based on Redundancy," Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, No. 2, pp. 194-206, Feb. 2009.

• 2007

• • Soontae Kim, N. Vijaykrishnan, and M. J. Irwin, "Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set Resolution," Microprocessors and Microsystems (MPMS), Vol. 31, No. 5, pp. 293-301, Aug. 2007.

• 2005

• • Soontae Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, "Exploiting Temporal Loads for Low Latency and High Bandwidth Memory," IEE Proceedings-Computers and Digital Techniques (CDT), Vol. 152, No. 4, pp. 457-466, July 2005.

• 2004

• • Soontae Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Optimizing Leakage Energy Consumption in Cache Bitlines," Design Automation for Embedded Systems (DAEM), Vol. 9, No. 1, pp. 5-18, March 2004.

  • A. Parikh, Soontae Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin, "Instruction Scheduling for Low Power," Journal of VLSI Signal Processing (JVLSI), Vol. 37, No. 1, pp. 129-149, May 2004.

  • J. Juran, A. R. Hurson, N. Vijaykrishnan, and Soontae Kim, "Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues," ACM/Kluwer Wireless Networks (WINET), Vol. 10, No. 2, pp. 183-195, March 2004.

  • Soontae Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Energy-Efficient Java Execution using Local Memory and Object Co-location," IEE Proceedings-Computers and Digital Techniques(CDT), Vol. 151, No. 1, pp. 33-42, January 2004.

• 2003

• • Soontae Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, and M. J. Irwin, "Partitioned Instruction Cache Architecture for Energy Efficiency," ACM Transactions on Embedded Computing Systems (TECS), Vol. 2, No. 2, pp. 163-185, May 2003.

Conferences

• 2023

  • Jinkwon Kim, Myeongjae Jang, Haejin Nam, and Soontae Kim, "HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator," IEEE/ACM International Symposium on Microarchitecture (MICRO'23).

• 2022

• • Myeongjae Jang, Jinkwon Kim, Jesung Kim, and Soontae Kim, "ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks,"  Design, Automation, and Test in Europe Conference (DATE'22).

  • Junoh Moon, Mincheol Kang, Wonyoung Lee, and Soontae Kim, "Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance," Design, Automation, and Test in Europe Conference (DATE'22).

  • Jinkwon Kim, Mincheol Kang, Jeongkyu Hong, and Soontae Kim, "Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data," IEEE International Symposium on High-Performance Computer Architecture (HPCA'22).

• 2020

• • Imran Fareed, Mincheol Kang, Wonyoung Lee, and Soontae Kim, "PAPA: Partial Page-aware Page Allocation in TLC Flash SSD for Performance Enhancement," International Conference on Massive Storage Systems and Technology (MSST'20), Oct. 29-30, 2020.

  • Imran Fareed, Mincheol Kang, Wonyoung Lee, and Soontae Kim, "Leveraging Intra-page Update Diversity for Mitigating Write Amplification in SSDs," International Conference on Supercomputing (ICS'20), Jun. 29 - Jul.2, 2020.

• 2018

• • Jeongkyu Hong, Hyeonggyu Kim, and Soontae Kim, "EAR: ECC-Aided Refresh Reduction through 2-D Zero Compression," International Conference on Parallel Architectures and Compilation Techniques (PACT'18), Limassol, Cyprus, Nov. 1-4, 2018. (36 papers accepted out of 126 submissions, 29% acceptance rate)

• 2017

• • Yebin Lee, Hyeonggyu Kim, Seokin Hong, and Soontae Kim, "Partial Row Activation for Low-Power DRAM System," IEEE International Symposium on High-Performance Computer Architecture (HPCA'17), Austin, TX, Feb. 4-8, 2017. (50 papers accepted out of 231 submissions, 21.6% acceptance rate)

• 2016

• • Minho Ju, Hyeonggyu Kim, and Soontae Kim, "MofySim: A Mobile Full System Simulation Framework for Energy Consumption and Performance Analysis," IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'16), Uppsala, Sweden, April 17-19, 2016. (35% acceptance rate)

  • Minho Ju, Hyeonggyu Kim, and Soontae Kim, "Network Delay-Aware Energy Management for Mobile Systems," Design, Automation, and Test in Europe Conference (DATE'16), Dresden, Germany, Mar. 14-18, 2016. (24% acceptance rate)

  • Minho Ju, Hyeonggyu Kim, and Soontae Kim, "Energy-Efficient Batch Scheduling for Background Network Services in Mobile Devices," IEEE International Conference on Consumer Electronics (ICCE'16), Las Vegas, NV, Jan. 8-11, 2016.

• 2015

• • Minho Ju*, Hyeonggyu Kim*, Mincheol Kang*, and Soontae Kim, "Efficient Memory Reclaiming for Mitigating Sluggish Response in Mobile Devices," IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin'15), Berlin, Germany, Sep. 6-9, 2015. (*equal contribution)

• 2014

• • Seokin Hong, Jongmin Lee, and Soontae Kim, "Ternary Cache: Three-valued MLC STT-RAM Caches," IEEE International Conference on Computer Design (ICCD'14), Seoul, Korea, Oct. 19-22, 2014. (63 papers accepted out of 202 submissions, 31% acceptance rate, Best Paper Nominee)

• 2013

• • Myoungjun Lee and Soontae Kim, "Performance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems," IEEE International Conference on Computer Design (ICCD'13),  Oct. 6-9, 2013, Asheville, NC, USA (79 papers accepted out of 223 submissions, 35% acceptance rate).

  • Seokin Hong and Soontae Kim, "AVICA: An Access-time Variation Insensitive L1 Cache Architecture," Design Automation and Test in Europe Conference (DATE’13), Grenoble, France, March 18 ~ 22 2013. (206 papers accepted out of 829 submissions, 24.8% acceptance rate, Best Paper Award)

  • Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee, "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low  Power," IEEE International Symposium on High-Performance Computer Architecture (HPCA'13), Feb. 23-27, 2013, Shenzhen, China (51 papers accepted out of 249 submissions, 20% acceptance rate)

  • Tayyeb Mahmood,  Soontae Kim, and Seokin Hong, "Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling," IEEE International Symposium on High-Performance Computer Architecture (HPCA'13), Feb. 23-27, 2013, Shenzhen, China (51 papers accepted out of 249 submissions, 20% acceptance rate)

• 2012

• • Jeongkyu Hong and Soontae Kim, "ECC String: Flexible ECC Management for Low-cost Error Protection of L2 Caches," IEEE International Conference on Computer Design (ICCD’12),  Sept. 30 ~ Oct. 3, 2012, Montreal, Canada (94 papers accepted out of 246 submissions, 38% acceptance rate).

  • Jongmin Lee and Soontae Kim, Adopting TLB Index-based Tagging to Data Caches for Tag Energy Reduction, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12), California, USA, Jul. 30 ~ Aug. 1, 2012 (66 papers accepted out of 213 submissions, 31% acceptance rate).

  • Sukki Kim, Soontae Kim, and Yebin Lee, DRAM Power-Aware Rank Scheduling, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12), California, USA, Jul. 30 ~ Aug. 1, 2012 (34 long papers accepted out of 213 submissions, 16% acceptance rate).

  • Tayyeb Mahmood and Soontae Kim. Near-Threshold Voltage Scaling in Last level Caches, International Exposition Yeosu Korea, International Conference on Information Technology (YSEC 2012), Suncheon, Korea, April 26~28, 2012 (Best Paper Award).

  • Mohammad Rouf and Soontae Kim. Control Flow Error Protection by Selective Re-execution and Available Redundancies in the Pipeline, International Exposition Yeosu Korea, International Conference on Information Technology (YSEC 2012), Suncheon, Korea, April 26~28, 2012.

  • Mohammad Rouf and Soontae Kim, Low-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline, Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC'12), Sydney, Australia, Jan. 30 ~ Feb. 2, 2012 ( 99 papers accepted out of 288 submissions, 34% acceptance rate).

• 2011

• • Kwangcheol Shin, Kyungjun Kim, and Soontae Kim, ADSR: Angle-based Multi-Hop Routing Strategy for Mobile Wireless Sensor Networks, IEEE Asia-Pacific Services Computing Conference (APSCC’11), Dec. 12~15, 2011, Jeju, Korea (69 papers accepted out of 273 submissions, 25.3% acceptance rate).

  • Soontae Kim, Jesung kim, Jongmin Lee, and Seokin Hong, Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits, In Proc. of IEEE/ACM International Symposium on Microarchitecture (MICRO’11), Dec. 3~7, 2011, Brazil (44 papers accepted out of 209 submissions, 21% acceptance rate).

  • Taeju Park and Soontae Kim. Dynamic Scheduling Algorithm and Its Schedulability Analysis for Certifiable Dual-Criticality Systems. In Proc. of International Conference on Embedded Software (EMSOFT’11), Taipei, Taiwan, Oct. 9~14, 2011 (27 papers accepted out of 111 submissions, 24.3% acceptance rate).

  • Tayyeb Mahmood and Soontae Kim. Realizing Near-True Voltage Scaling in Variation-Sensitive L1 Caches via Fault Buffers. In Proc. of International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES’11), Taipei, Taiwan, Oct. 9~14, 2011 (23 papers accepted out of 61 submissions, 37.7% acceptance rate, Best Paper Nominee).

  • Sukki Kim and Soontae Kim. Operating System-Directed DRAM Refresh Energy Reduction. In Proc. of Triangle Symposium on Advanced ICT (TRISAI’11), Aug. 25~26, Korea.

  • Jongmin Lee, Seokin Hong, Soontae Kim. TLB Index-based Tagging for Cache Energy Reduction (long paper), ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, Aug. 1~3, 2011 ( 30 long papers, 45 regular papers accepted out of 201 submissions, 14.9% and 22.4% acceptance rates, respectively).

  • Yebin Lee, Soontae Kim. DRAM energy reduction by prefetching-based memory traffic clustering (long paper). ACM Great Lakes Symposium on VLSI (GLSVLSI’11), Rosanne, Switzerland, May 2~4, 2011 (35 long papers, 57 regular papers accepted out of 207 submissions, 16.9% and 27% acceptance rates, respectively).

• 2010

• • Divyan M. Konidala, Made H. Dwijaksara, Kwangjo Kim, Byoungcheon Lee, Daeyoung Kim, Soontae Kim, Dongman Lee, "Resuscitating Privacy-Preserving Mobile Payment with Customer in Complete Control," International Workshop on Smartphone Applications and Services (Smartphone’10), 2010.

  • Taeju Park and Soontae Kim, "Performance modeling using hardware performance counters," Triangle Symposium on Advanced ICT (TRISAI’10), Oct. 25~27, China (Best Paper Award).

  • Seokin Hong, Soontae Kim. Lizard: energy-efficient hard fault detection, diagnosis and isolation in the ALU (long paper). IEEE International Symposium on Computer Design (ICCD’10), Amsterdam, Netherlands, Oct. 3~6, 2010. (79 papers accepted out of 267 submissions, 29% acceptance rate, Best Paper Award).

  • Mohammad Rouf and Soontae Kim. Modeling and evaluation of control flow vulnerability in the embedded system. In Proc. of IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems(MASCOTS'10), Miami, Florida, USA, Aug. 17~19, 2010 (A poster paper. Only best papers not accepted as standard papers are invited as poster papers, 36 standard papers accepted out of 119 submissions).

  • Tayyeb Mahmood and Soontae Kim. Fine-grained fault tolerance for process variation-aware caches. IEEE computer Society Annual International Symposium on VLSI (ISVLSI’10), Lixouri Kefalonia, Greece, July 5~7, 2010. (75 regular papers accepted out of 278 submissions, 27% acceptance rate)

  • Soontae Kim and Jongmin Lee. Write buffer-oriented energy reduction in the data cache of two-level caches for the embedded systems. ACM Great Lakes Symposium on VLSI (GLSVLSI’10), Providence, USA, May 16~18, 2010. (50 regular papers accepted out of 165 submissions, 30% acceptance rate)

  • Jesung kim, Soontae Kim, Yebin Lee. SimTag: Exploiting Tag Bits Similarity to Improve the Reliability of the Data Caches. Proc. of Design Automation and Test in Europe Conference (DATE’10), Dresden, Germany, March 8~12 2010. (30% acceptance rate)

  • Sangjae Lee, Sunghee Lee, Youngae Jeon, Sangsung Choi, and Soontae Kim, High Definition Video Transmission using Bluetooth over UWB. IEEE International Conference on Consumer Electronics (ICCE’10), Jan. 9~13, 2010, Las Vegas, USA (44% acceptance rate).

• 2009

• • Yebin Lee, Soontae Kim, Impact of DRAM Power Down Mode on System Performance and Energy Consumption, In Proc. of  Triangle Symposium on Advanced ICT (TRISAI 2009), Oct. 28~30, Tokyo, Japan.

  • Jongmin Lee, Soontae Kim, Energy-delay efficient 2-level data cache architecture for embedded systems. In Proc. of  ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’09), San Francisco, CA, USA, Aug. 2009 (75 papers accepted out of 210 submissions, 35.7% acceptance rate).

  • Seokin Hong, Soontae Kim, TEPS: Transient error protection utilizing sub-word parallelism. In Proc. of IEEE computer Society Annual International Symposium on VLSI (ISVLSI’09), Tampa, FL, USA, May 13-15 2009 (34 regular papers out of 138 submissions, 24.6% acceptance rate).

• 2007

• • K. Bhattacharya, Soontae Kim, N. Ranganathan. Improving the reliability of on-chip L2 cache using redundancy. In Proc. of IEEE International Conference on Computer Design (ICCD’07), Lake Tahoe, CA, USA, Oct. 7-10 2007 (28% acceptance rate).

  • Soontae Kim. Reducing ALU and Register File Energy by Dynamic Zero Detection. Proc. of International Performance Computing and Communication Conference (IPCCC’07), New Orleans, Louisiana, USA, April 11-13 2007 (44 papers out of 119 submissions, 37% acceptance rate).

• 2006

• • Soontae Kim. Area-Efficient Error Protection for Caches. In Proc. of Design, Automation and Test in Europe (DATE’06), Munich, Germany, March 2006 (233 regular papers out of 834 submissions, 28% acceptance rate).

• 2004

• • J. S. Hu, N. Vijaykrishnan, Soontae Kim, M. Kandemir, and M. J. Irwin. Scheduling Reusable Instructions for Power Reduction. In Proc. of Design, Automation and Test in Europe (DATE’04), Paris, France, Feb. 2004 (181 regular papers accepted out of 780 submissions, 23% acceptance rate).

• 2003

• • Soontae Kim, N. Vijaykrishnan, M. J. Irwin, and L. K. John. On Load Latency in Low-Power Caches. In Proc. of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’03), pp. 258-261, Seoul, Korea, Aug. 2003 (90 papers accepted out of 221 submissions, 41% acceptance rate).

  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, Soontae Kim, and W. Zhang. Masking the Energy Behavior of DES encryption (long paper). In Proc. of Design, Automation and Test in Europe Conference (DATE’03), pp. 84-89, Munich, Germany, Mar. 2003 (best paper nominee, 98 long papers and 152 regular papers accepted out of 590 submissions, 17% and 25.8% acceptance rates, respectively).

• 2002

• • Soontae Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Predictive Precharging for Bitline Leakage Energy Reduction. In Proc. of Annual IEEE International ASIC/SOC Conference (ASIC/SOC’02), pp. 36-40, Rochester, NY, Sep. 2002.

• 2001

• • Soontae Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Energy-Efficient Instruction Cache Using Page-Based Placement. In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’01), pp. 229-237, Atlanta, GA, Nov. 2001 (28 papers accepted out of 80 submissions, 35% acceptance rate).

  • S. Tomar, Soontae Kim, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Use of Local Memory for Efficient Java Execution. In Proc. of IEEE International Conference on Computer Design (ICCD’01), pp. 468-473, Austin, Texas, Sep. 2001 (61 papers accepted out of 181 submissions, 34% acceptance rate).

  • Soontae Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, and E. Geethanjali. Power aware Partitioned Cache Architectures. In Proc. of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’01), pp. 64-67, Huntington Beach, CA, Aug. 2001 (73 papers accepted out of 194 submissions, 38% acceptance rate).

  • N.Vijaykrishnan, M. Kandemir, Soontae Kim, S. Tomar, A. Sivasubramaniam, and M. J. Irwin. Energy Behavior of Java Applications from the Memory Perspective. In Proc. of USENIX Virtual Machine Research and Technology Symposium (VM’01), pp. 207-220, Monterey, CA, Apr. 2001 (18 papers accepted out of 50 submissions, 36% acceptance rate).

Domestic Publications

• 2017

• • 강민철, 이명준, 김순태, "소형 무인기 탐지 FMCW 레이다 시스템을 위한 Leakage 및 클러터 제거 기법," 국방SW연구회 추계 워크샵, 2017년 11월 13일, 코엑스, 서울.

  • Ryunkyun Park, Jesung Kim, Soontae Kim, "Reducing Display Energy Consumption for Android Display Based on On-Chip Framebuffer Cache," in Proc. of Korea Computer Congress (KCC), June 2017, Jeju, Korea.

• 2015

• • Minho Ju, Hyeonggyu Kim, and Soontae Kim, "Energy Consumption and Performance Analysis Method under the Network Condition based on Mobile Full System Simulation," In Proc. of Korea Computer Congress (KCC), June 2015, Jeju, Korea.

• 2010

• • Jongmin Lee and Soontae Kim, "Energy-delay efficient 2-level data cache architecture for embedded system," Journal of KIISE, Oct. 2010.

  • Taejoo Park and Soontae Kim, "System performance modeling for prediction of deadline misses," In Proc. of Workshop on Dependable Computing System, Aug. 2010, Jeju, Korea.

• 2008

• • Jongmin Lee, Soontae Kim, et al., "Low-Power 2-level Cache Architectures for Embedded system," KIPS Fall Conference, 2008.

• 1998

• • S. Kim, D. Kim, and S. Han, "DCRS: a Cell Library Characterization System," Journal of KISS(c): Computing Practices, Vol. 4, No. 5, pp. 55-761, Oct. 1998.

• 1997

• • S. Kim and S. Han, "Minimizing Timing Error in Generating Characterization Table," KISS Fall Conference, Korea, 1997.

  • S. Kim and S. Han, "Optimal Characterization Table Generating System," KISS Spring Conference, Korea, 1997.