About me
Born in Gujranwala (Dec-1983) to a Kashmiri (Butt) family, I love eating. But I also have keen interest in science, unnaturally. The only possible reason for this anomaly seems to be a Gene mutation. I weigh 85KG at the time of writing (Nov-2012) and was about 91 KG at the start of 2012. I aim to weigh about 76KG at the time of graduation.
Computer
After a vocational computer course, my father bought me a Desktop in 1999. It was Pentium I 333MHz processor with 32MB SDRAM and 3GB harddisk, with a price tag of $300. As of 2012, our handsets are much more powerful than this machine.
Software
In 2001, I learned "Visual Basic" to make Windows 98 screen savers. However, I found programming very interesting and decided to pursue Software engineering. But my teachers guided me that Electrical Engineering would be more appropriate because I could also learn how to design a computer itself.
Digital Design and VLSI
In 2001, I joined BSEE track in University of Engineering and technology, Lahore and learned Java in first semester. In semester break, I learned x86 Assembly and 8051 microcontrollers. It was fun and four years were passed from term project to term project, each using microcontrollers in different ways.
Internship at KICS
During summer break of 2005, I joined SDR Lab at KICS as Research Assistant. I was assigned the schematics of an SDR having an ARM microcontroller, a TI DSP and a XILINX FPGA. Here, I came closer to Verilog HDL and my romance with Digital design started because I was a software meant to be hardware.
Job at CARE
After graduation, I joined CARE in DEC 2005. Here, my work was related to the front end of another SDR. As the core platform engineer, I worked with ADCs, digital down converters and FPGA. I also designed Digital Filters including FIR filters for Automatic gain controllers and IIR filters (with pipeline compensation) for Automatic tuners. I also designed Test generators with Agilent and Tektonix equipment and assisted Software designers for bootstrap procedures and GUI.
Job at RCET
In Feb 2007, I joined RCET as a junior Lecturer in Electrical Engineering Department and performed many teaching assignments related to Microprocessors, Communications and Control systems.
PhD at KAIST ...
I joined ECL with an integrated MS/PhD track in Spring 2008. My work here is mostly related to cache design for low power. Today, manufacturers integrate many MBs of cache in there processors which leaks watts of power. The only way to avoid it is to lower the voltage. However, one cannot do it without sacrificing cache reliability because caches are protected with the same voltage guard bands. My work belongs to the class of architectural schemes which reclaim this cache reliability on low voltage.
List of my publications is given below.
Below is the list of Major courses I studied during my academic career in KAIST.
2008
26.502 Computer Architecture A+
26.581 Intro. to SoC A0
26.630 Video Coding Theory B+
2009
35.414 Embedded systems A-
35.574 CAD of VLSI Circuits & Systems A0 (Best term project: Power-aware technology mapping
in SIS)
36.710 Topics in CA (Fault-tolerant computing) A- (Term project extended to publication in ISVLSI'10)
2010
35.678 Digital integrated circuits A0
42.454 Information policy (Smart, Green and Soft Korea) A0
2011
36.410 Intro. VLSI Design (NoC Architecture) A+ (Best term project: A Radix-10 router design
& implementation in 45nm TSMC using
Synopsys DC/IC)
35.774 VLSI Design Methodology (Topics) A+ (Best term project: Network interface design for
Many-Core OPENRISC Architecture)